EN PCI Express (PCIe) Clock Buffers, PCI Express (PCIe) Clock Generators, Jitter Attenuator, and Automotive Compliant PCIe 4.0 Clock Generators and Clock Buffers. More
Μετάφραση "clock tower" σε κινέζικα
Εμφάνιση 50 από 50 μεταφράσεις της φράσης "clock tower" από Αγγλικά σε κινέζικα
Μετάφραση του Αγγλικά σε κινέζικα του clock tower
Αγγλικά
κινέζικα
ZH 包含PCI Express (PCIe) 時脈緩衝器、PCI Express (PCIe) 時脈產生器和 HiFlex 時鐘產生器。 More
Μεταγραφή bāo hánPCI Express (PCIe) shí mài huǎn chōng qì、PCI Express (PCIe) shí mài chǎn shēng qì hé HiFlex shí zhōng chǎn shēng qì。 More
| Αγγλικά | κινέζικα |
|---|---|
| pci | pci |
| pcie | pcie |
EN Timing Solutions ICs like Clock Buffers, Clock Generators, Clock Synthesizer and Real Time Clocks (RTC). More
ZH 時鐘IC解決方案包含時鐘緩衝器、時鐘產生器、時鐘合成器和即時時鐘(RTC)。 More
Μεταγραφή shí zhōngIC jiě jué fāng àn bāo hán shí zhōng huǎn chōng qì、 shí zhōng chǎn shēng qì、 shí zhōng hé chéng qì hé jí shí shí zhōng (RTC)。 More
EN Military green with luminous Arabic numerals and hour markers. Date at 3 o'clock, power reserve indicator at 5 o'clock, 24h indicator at 9 o'clock
ZH 軍綠色，附夜光阿拉伯數字及小時標示。3點鐘位置設日期顯示，5點鐘位置設動力儲存顯示，9點鐘位置設24小時顯示
Μεταγραφή jūn lǜ sè， fù yè guāng ā lā bó shù zì jí xiǎo shí biāo shì。3diǎn zhōng wèi zhì shè rì qī xiǎn shì，5diǎn zhōng wèi zhì shè dòng lì chǔ cún xiǎn shì，9diǎn zhōng wèi zhì shè24xiǎo shí xiǎn shì
EN The Renesas clock generators or clock synthesizer products support several different type of differential clock output levels such as LVPECL, LVDS, HCSL etc.
ZH Renesas’ 的时钟发生器或时钟合成器产品支持多种不同类型的差分时钟输出等级，如 LVPECL、LVDS、HCSL 等。 与这些差分时钟有关的应用说明可从数据表和本网站中获取。
Μεταγραφή Renesas’ de shí zhōng fā shēng qì huò shí zhōng hé chéng qì chǎn pǐn zhī chí duō zhǒng bù tóng lèi xíng de chà fēn shí zhōng shū chū děng jí， rú LVPECL、LVDS、HCSL děng。 yǔ zhè xiē chà fēn shí zhōng yǒu guān de yīng yòng shuō míng kě cóng shù jù biǎo hé běn wǎng zhàn zhōng huò qǔ。
EN Ansys Clock FX software for IC design performs fast, SPICE-accurate transistor level timing analysis on Clock Trees and Clock Meshes in the design with voltage and temperature variability using a single library model.
ZH 適用於 IC 設計的 Ansys Clock FX 軟體使用單一程式庫模型?在電壓與溫度會變化的設計中?針對時脈樹和時鐘網格 執行快速、具 SPICE 準確度的電晶體層級時序分析。
Μεταγραφή shì yòng yú IC shè jì de Ansys Clock FX ruǎn tǐ shǐ yòng dān yī chéng shì kù mó xíng? zài diàn yā yǔ wēn dù huì biàn huà de shè jì zhōng? zhēn duì shí mài shù hé shí zhōng wǎng gé zhí xíng kuài sù、 jù SPICE zhǔn què dù de diàn jīng tǐ céng jí shí xù fēn xī。
EN Ansys Clock FX evaluates all the clock paths in an SoC for clock jitter caused by Supply Noise Variation.
ZH Ansys Clock FX 會評估 SoC 中所有時脈路徑?是否有供應雜訊變化所造成的時脈抖動。
Μεταγραφή Ansys Clock FX huì píng gū SoC zhōng suǒ yǒu shí mài lù jìng? shì fǒu yǒu gōng yīng zá xùn biàn huà suǒ zào chéng de shí mài dǒu dòng。
EN Ansys Clock FX automatically identifies and simulates all the clock paths in a design and can account for all critical contributors to clock jitter in each path across multiple processes, voltages, temperature corners and scenarios.
ZH Ansys Clock FX 會自動確認並模擬設計中所有時脈路徑?並可以說明在多種製程、電壓、溫度邊界和情境中每條路徑發生時脈抖動的所有關鍵因素。
Μεταγραφή Ansys Clock FX huì zì dòng què rèn bìng mó nǐ shè jì zhōng suǒ yǒu shí mài lù jìng? bìng kě yǐ shuō míng zài duō zhǒng zhì chéng、 diàn yā、 wēn dù biān jiè hé qíng jìng zhōng měi tiáo lù jìng fā shēng shí mài dǒu dòng de suǒ yǒu guān jiàn yīn sù。
EN Ansys Clock FX is an add-on to existing sign-off flows, with the performance needed to evaluate all clock paths in an SoC for clock jitter on even the largest designs.
ZH Ansys Clock FX 是現有簽核流程的附加元件?其效能足以評估 SoC 中所有時脈路徑中是否有時脈抖動?即使是最大的設計也沒問題。
Μεταγραφή Ansys Clock FX shì xiàn yǒu qiān hé liú chéng de fù jiā yuán jiàn? qí xiào néng zú yǐ píng gū SoC zhōng suǒ yǒu shí mài lù jìng zhōng shì fǒu yǒu shí mài dǒu dòng? jí shǐ shì zuì dà de shè jì yě méi wèn tí。
EN time time and date time icon vector illustration calendar calendar clock clock
ZH 倒数 分钟 加载 处理 处理中 天文台 小时 开始 时钟 时间
Μεταγραφή dào shù fēn zhōng jiā zài chù lǐ chù lǐ zhōng tiān wén tái xiǎo shí kāi shǐ shí zhōng shí jiān
EN time time and date time calendar calendar clock clock date schedule icon
ZH 倒数 分钟 加载 处理 处理中 天文台 小时 开始 时钟 时间
Μεταγραφή dào shù fēn zhōng jiā zài chù lǐ chù lǐ zhōng tiān wén tái xiǎo shí kāi shǐ shí zhōng shí jiān
EN time time and date time calendar icon vector illustration calendar clock clock
ZH 倒数 分钟 加载 处理 处理中 天文台 小时 开始 时钟 时间
Μεταγραφή dào shù fēn zhōng jiā zài chù lǐ chù lǐ zhōng tiān wén tái xiǎo shí kāi shǐ shí zhōng shí jiān
EN clock clock time time hour watch timer time and date minute countdown
ZH 倒数 分钟 历史 发条 可爱的应用程序图标 审美应用程序图标 小时 常规 应用 应用程式图示
Μεταγραφή dào shù fēn zhōng lì shǐ fā tiáo kě ài de yīng yòng chéng xù tú biāo shěn měi yīng yòng chéng xù tú biāo xiǎo shí cháng guī yīng yòng yīng yòng chéng shì tú shì
EN Known issue: Ryzen CPUs will still show clock speed as '-1' in 3DMark and VRMark until next benchmark update due to Ryzen CPUs not having a "stock clock" value for CPUID to read.
ZH 已知问题：由于 Ryzen CPU 无 CPUID 可读取的原始时脉值，因此在下一次基准更新前，Ryzen CPU 仍然会在 3DMark 和 VRMark 中显示时脉为 “-1”。
Μεταγραφή yǐ zhī wèn tí： yóu yú Ryzen CPU wú CPUID kě dú qǔ de yuán shǐ shí mài zhí， yīn cǐ zài xià yī cì jī zhǔn gèng xīn qián，Ryzen CPU réng rán huì zài 3DMark hé VRMark zhōng xiǎn shì shí mài wèi “-1”。
EN Alarm Clock Xtreme: Sleep better & wake up easier with our smart alarm clock
ZH 已經有超過 5000 萬人使用我們的鬧鐘。
Μεταγραφή yǐ jīng yǒu chāo guò 5000 wàn rén shǐ yòng wǒ men de nào zhōng。
EN Click Analog Clock to turn off the screen. Table Clock
ZH 單擊模擬時鐘以關閉屏幕。台鐘
Μεταγραφή dān jī mó nǐ shí zhōng yǐ guān bì píng mù。tái zhōng
EN Automotive Compliant PCIe 4.0 Clock Generators and Clock Buffers
ZH 車用規格PCIe4.0時鐘產生器/合成器
Μεταγραφή chē yòng guī géPCIe4.0shí zhōng chǎn shēng qì/hé chéng qì
EN Real Time Clock (RTC) provides high accuracy at low voltage (1.2 V) in smallest 4X4mm DFN. Calendar/ clock, data storage functions. I2C and 3-Wire Interface. More
ZH Diodes 的 RTC（即時時鐘）電路在特殊應用積體電路中，提供月曆 / 時鐘和資料儲存功能。 More
Μεταγραφή Diodes de RTC （jí shí shí zhōng） diàn lù zài tè shū yīng yòng jī tǐ diàn lù zhōng， tí gōng yuè lì / shí zhōng hé zī liào chǔ cún gōng néng。 More
EN CodeGuru profiles CPU (active CPU and wall clock time) and memory (heap summary) for Java and other JVM languages and CPU (wall clock time) for Python applications.
ZH CodeGuru 分析 Java和其他 JVM 語言的 CPU (作用中 CPU 和真實時鐘時間) 與記憶體 (堆積摘要)，以及 Python 應用程式的 CPU (真實時鐘時間)。
Μεταγραφή CodeGuru fēn xī Java hé qí tā JVM yǔ yán de CPU (zuò yòng zhōng CPU hé zhēn shí shí zhōng shí jiān) yǔ jì yì tǐ (duī jī zhāi yào)， yǐ jí Python yīng yòng chéng shì de CPU (zhēn shí shí zhōng shí jiān)。
| Αγγλικά | κινέζικα |
|---|---|
| java | java |
| python | python |
EN Known issue: Ryzen CPUs will still show clock speed as '-1' in 3DMark and VRMark until next benchmark update due to Ryzen CPUs not having a "stock clock" value for CPUID to read.
ZH 已知问题：由于 Ryzen CPU 无 CPUID 可读取的原始时脉值，因此在下一次基准更新前，Ryzen CPU 仍然会在 3DMark 和 VRMark 中显示时脉为 “-1”。
Μεταγραφή yǐ zhī wèn tí： yóu yú Ryzen CPU wú CPUID kě dú qǔ de yuán shǐ shí mài zhí， yīn cǐ zài xià yī cì jī zhǔn gèng xīn qián，Ryzen CPU réng rán huì zài 3DMark hé VRMark zhōng xiǎn shì shí mài wèi “-1”。
EN The II will increase if the target clock frequency is too high and the FPGA fabric routing paths are simply too long to meet the timing requirement. A solution to this problem would be to split logic into two paths running at half the clock frequency.
ZH 如果目標時鐘頻率太高，並且FPGA結構路由路徑太長而無法滿足時序要求，則II將增加。這個問題的解決方案是將邏輯分成兩條以時鐘頻率一半運行的路徑。
Μεταγραφή rú guǒ mù biāo shí zhōng pín lǜ tài gāo， bìng qiěFPGA jié gòu lù yóu lù jìng tài zhǎng ér wú fǎ mǎn zú shí xù yào qiú， zéII jiāng zēng jiā。zhè gè wèn tí de jiě jué fāng àn shì jiāng luó jí fēn chéng liǎng tiáo yǐ shí zhōng pín lǜ yī bàn yùn xíng de lù jìng。
EN This demo shows how integrated clock generators can be used to create all the clock needed by a system. This particular example shows our Renesas R-Car SoC, but the example applies to any kind of electronic system.
ZH 此演示展示了如何使用集成时钟发生器，来创建系统所需的所有时钟。 这个特定只示例展示了瑞萨的 R-Car 系列 SoC，但该示例适用于任何类型的电子系统。
Μεταγραφή cǐ yǎn shì zhǎn shì le rú hé shǐ yòng jí chéng shí zhōng fā shēng qì， lái chuàng jiàn xì tǒng suǒ xū de suǒ yǒu shí zhōng。 zhè gè tè dìng zhǐ shì lì zhǎn shì le ruì sà de R-Car xì liè SoC， dàn gāi shì lì shì yòng yú rèn hé lèi xíng de diàn zi xì tǒng。
EN New Clock Buffers and Multiplexers join clock generators to complete the PCIe timing portfolio and together deliver 40 fs RMS surpassing the PCIe Gen6 100 fs specification
ZH 适用于高性能 CPU 和 SoC 的计时解决方案
Μεταγραφή shì yòng yú gāo xìng néng CPU hé SoC de jì shí jiě jué fāng àn
EN Clock ICs and Clock Timing Solutions
ZH 时钟 IC 和时钟时序解决方案
Μεταγραφή shí zhōng IC hé shí zhōng shí xù jiě jué fāng àn
EN About Clock Generators and Frequency Synthesizers (Clock Synthesizers)
ZH 关于时钟发生器和频率合成器（时钟合成器）
Μεταγραφή guān yú shí zhōng fā shēng qì hé pín lǜ hé chéng qì （shí zhōng hé chéng qì）
EN Supports IEEE 1588 and Synchronous Ethernet communication requirements. PTP Clock Manager features a clock servo and Packet Delay Variation (PDV) filter to meet the needs for G.8275.1 and G.8275.2 standards from the ITU-T.
ZH 支持 IEEE 1588 和同步以太网通信要求。 PTP Clock Manager 具备时钟伺服和数据包延迟变化 (PDV) 滤波器，可满足 ITU-T 标准 G.8273.4 和 G.8263 的需求。
Μεταγραφή zhī chí IEEE 1588 hé tóng bù yǐ tài wǎng tōng xìn yào qiú。 PTP Clock Manager jù bèi shí zhōng cì fú hé shù jù bāo yán chí biàn huà (PDV) lǜ bō qì， kě mǎn zú ITU-T biāo zhǔn G.8273.4 hé G.8263 de xū qiú。
| Αγγλικά | κινέζικα |
|---|---|
| ieee | ieee |
| g | g |
EN Clock tree design can be a complex task with many considerations that are often overwhelming to designers unfamiliar with clock trees and the associated “language” of timing.
ZH 时钟树设计是一项复杂的任务，需要考虑的问题繁多，往往令不熟悉时钟树和相关的计时“语言”的设计师望而生畏。
Μεταγραφή shí zhōng shù shè jì shì yī xiàng fù zá de rèn wù， xū yào kǎo lǜ de wèn tí fán duō， wǎng wǎng lìng bù shú xī shí zhōng shù hé xiāng guān de jì shí “yǔ yán” de shè jì shī wàng ér shēng wèi。
EN Simulate Delays and Clock Jitter on the Clock Paths
ZH 模擬時脈路徑上的延遲和時脈抖動
Μεταγραφή mó nǐ shí mài lù jìng shàng de yán chí hé shí mài dǒu dòng
EN May Tower is a/an Estate located at Mid-Levels Central. May Tower was built in 1992 consists of 2 blocks and has a total of 79 units. May Tower is located in School Net 11.
ZH 梅苑是位于中半山的屋苑，于1992年落成，共建有2座及79个单位。梅苑位处11校网。
Μεταγραφή méi yuàn shì wèi yú zhōng bàn shān de wū yuàn， yú1992nián luò chéng， gòng jiàn yǒu2zuò jí79gè dān wèi。méi yuàn wèi chù11xiào wǎng。
EN Suncrest Tower is a/an Estate located at Mid-Levels Central. Suncrest Tower was built in 1986. Suncrest Tower is located in School Net 12.
ZH Suncrest Tower是位于Mid-Levels Central的Estate，于1986年落成。Suncrest Tower位处12校网。
Μεταγραφή Suncrest Tower shì wèi yúMid-Levels Central deEstate， yú1986nián luò chéng。Suncrest Tower wèi chù12xiào wǎng。
EN May Tower Block 2 is a/an Estate located at Mid-Levels Central. May Tower Block 2 was built in 1992 consists of 25 floors and has a total of 25 units. May Tower Block 2 is located in School Net 11.
ZH 梅苑 2座是位于中半山的屋苑，于1992年落成，共建有25层及25个单位。梅苑 2座位处11校网。
Μεταγραφή méi yuàn 2zuò shì wèi yú zhōng bàn shān de wū yuàn， yú1992nián luò chéng， gòng jiàn yǒu25céng jí25gè dān wèi。méi yuàn 2zuò wèi chù11xiào wǎng。
EN The Royal Tower is a/an Estate located at Mid-Levels Central. The Royal Tower was built in 1993. The Royal Tower is located in School Net 11.
ZH The Royal Tower是位于Mid-Levels Central的Estate，于1993年落成。The Royal Tower位处11校网。
Μεταγραφή The Royal Tower shì wèi yúMid-Levels Central deEstate， yú1993nián luò chéng。The Royal Tower wèi chù11xiào wǎng。
EN Dynasty Court Tower 1 is a/an Estate located at Mid-Levels Central. Dynasty Court Tower 1 was built in 1991 consists of 40 floors and has a total of 79 units. Dynasty Court Tower 1 is located in School Net 11.
ZH 帝景園 1 座是位于中半山的屋苑，于1991年落成，共建有40层及79个单位。帝景園 1 座位处11校网。
Μεταγραφή dì jǐng yuán 1 zuò shì wèi yú zhōng bàn shān de wū yuàn， yú1991nián luò chéng， gòng jiàn yǒu40céng jí79gè dān wèi。dì jǐng yuán 1 zuò wèi chù11xiào wǎng。
EN Dynasty Court Tower 2 is a/an Estate located at Mid-Levels Central. Dynasty Court Tower 2 was built in 1991 consists of 44 floors and has a total of 87 units. Dynasty Court Tower 2 is located in School Net 11.
ZH 帝景园 2 座是位于中半山的屋苑，于1991年落成，共建有44层及87个单位。帝景园 2 座位处11校网。
Μεταγραφή dì jǐng yuán 2 zuò shì wèi yú zhōng bàn shān de wū yuàn， yú1991nián luò chéng， gòng jiàn yǒu44céng jí87gè dān wèi。dì jǐng yuán 2 zuò wèi chù11xiào wǎng。
EN Regent on the Park Tower 2 is a/an Estate located at Mid-Levels Central. Regent on the Park Tower 2 was built in 1985 consists of 34 floors and has a total of 67 units. Regent on the Park Tower 2 is located in School Net 11.
ZH Regent on the Park Tower 2是位于Mid-Levels Central的Estate，于1985年落成，共建有34层及67个单位。Regent on the Park Tower 2位处11校网。
Μεταγραφή Regent on the Park Tower 2shì wèi yúMid-Levels Central deEstate， yú1985nián luò chéng， gòng jiàn yǒu34céng jí67gè dān wèi。Regent on the Park Tower 2wèi chù11xiào wǎng。
| Αγγλικά | κινέζικα |
|---|---|
| of | 的 |
EN Regent on the Park Tower 1 is a/an Estate located at Mid-Levels Central. Regent on the Park Tower 1 was built in 1985 consists of 36 floors and has a total of 70 units. Regent on the Park Tower 1 is located in School Net 11.
ZH Regent on the Park Tower 1是位于Mid-Levels Central的Estate，于1985年落成，共建有36层及70个单位。Regent on the Park Tower 1位处11校网。
Μεταγραφή Regent on the Park Tower 1shì wèi yúMid-Levels Central deEstate， yú1985nián luò chéng， gòng jiàn yǒu36céng jí70gè dān wèi。Regent on the Park Tower 1wèi chù11xiào wǎng。
| Αγγλικά | κινέζικα |
|---|---|
| of | 的 |
EN Century Tower 2 is a/an Estate located at Mid-Levels Central. Century Tower 2 was built in 1971 consists of 22 floors and has a total of 22 units. Century Tower 2 is located in School Net 11.
ZH 世紀大厦 2座是位于中半山的屋苑，于1971年落成，共建有22层及22个单位。世紀大厦 2座位处11校网。
Μεταγραφή shì jì dà shà 2zuò shì wèi yú zhōng bàn shān de wū yuàn， yú1971nián luò chéng， gòng jiàn yǒu22céng jí22gè dān wèi。shì jì dà shà 2zuò wèi chù11xiào wǎng。
EN Century Tower 1 is a/an Estate located at Mid-Levels Central. Century Tower 1 was built in 1971 consists of 30 floors and has a total of 60 units. Century Tower 1 is located in School Net 11.
ZH 世紀大厦 1座是位于中半山的屋苑，于1971年落成，共建有30层及60个单位。世紀大厦 1座位处11校网。
Μεταγραφή shì jì dà shà 1zuò shì wèi yú zhōng bàn shān de wū yuàn， yú1971nián luò chéng， gòng jiàn yǒu30céng jí60gè dān wèi。shì jì dà shà 1zuò wèi chù11xiào wǎng。
EN Regence Royale Tower 2 is a/an Estate located at Mid-Levels Central. Regence Royale Tower 2 was built in 2001 consists of 27 floors and has a total of 54 units. Regence Royale Tower 2 is located in School Net 11.
ZH 富汇豪庭 2座是位于中半山的屋苑，于2001年落成，共建有27层及54个单位。富汇豪庭 2座位处11校网。
Μεταγραφή fù huì háo tíng 2zuò shì wèi yú zhōng bàn shān de wū yuàn， yú2001nián luò chéng， gòng jiàn yǒu27céng jí54gè dān wèi。fù huì háo tíng 2zuò wèi chù11xiào wǎng。
EN Tregunter Tower 2 is a/an Estate located at Mid-Levels Central. Tregunter Tower 2 was built in 1981 consists of 32 floors and has a total of 64 units. Tregunter Tower 2 is located in School Net 11.
ZH 地利根德阁 2座是位于中半山的屋苑，于1981年落成，共建有32层及64个单位。地利根德阁 2座位处11校网。
Μεταγραφή de lì gēn dé gé 2zuò shì wèi yú zhōng bàn shān de wū yuàn， yú1981nián luò chéng， gòng jiàn yǒu32céng jí64gè dān wèi。de lì gēn dé gé 2zuò wèi chù11xiào wǎng。
EN Tregunter Tower 3 is a/an Estate located at Mid-Levels Central. Tregunter Tower 3 was built in 1993 consists of 49 floors and has a total of 187 units. Tregunter Tower 3 is located in School Net 11.
ZH 地利根德阁 3座是位于中半山的屋苑，于1993年落成，共建有49层及187个单位。地利根德阁 3座位处11校网。
Μεταγραφή de lì gēn dé gé 3zuò shì wèi yú zhōng bàn shān de wū yuàn， yú1993nián luò chéng， gòng jiàn yǒu49céng jí187gè dān wèi。de lì gēn dé gé 3zuò wèi chù11xiào wǎng。
EN Conduit Tower is a/an Stand-alone Building located at Mid-Levels West. Conduit Tower was built in 1992 consists of 1 blocks, 27 floors and has a total of 108 units. Conduit Tower is located in School Net 11.
ZH Conduit Tower是位于Mid-Levels West的Stand-alone Building，于1992年落成，共建有1座，27层及108个单位。Conduit Tower位处11校网。
Μεταγραφή Conduit Tower shì wèi yúMid-Levels West deStand-alone Building， yú1992nián luò chéng， gòng jiàn yǒu1zuò，27céng jí108gè dān wèi。Conduit Tower wèi chù11xiào wǎng。
| Αγγλικά | κινέζικα |
|---|---|
| of | 的 |
EN Corona Tower is a/an Stand-alone Building located at Mid-Levels West. Corona Tower was built in 1990 consists of 1 blocks, 28 floors and has a total of 220 units. Corona Tower is located in School Net 11.
ZH 嘉景台是位于西半山的单幢式大厦，于1990年落成，共建有1座，28层及220个单位。嘉景台位处11校网。
Μεταγραφή jiā jǐng tái shì wèi yú xī bàn shān de dān chuáng shì dà shà， yú1990nián luò chéng， gòng jiàn yǒu1zuò，28céng jí220gè dān wèi。jiā jǐng tái wèi chù11xiào wǎng。
EN Skylight Tower is a/an Estate located at Mid-Levels West. Skylight Tower was built in 1990 consists of 1 blocks, 31 floors and has a total of 62 units. Skylight Tower is located in School Net 11.
ZH 嘉丽苑是位于西半山的屋苑，于1990年落成，共建有1座，31层及62个单位。嘉丽苑位处11校网。
Μεταγραφή jiā lì yuàn shì wèi yú xī bàn shān de wū yuàn， yú1990nián luò chéng， gòng jiàn yǒu1zuò，31céng jí62gè dān wèi。jiā lì yuàn wèi chù11xiào wǎng。
EN Caine Tower is a/an Stand-alone Building located at Mid-Levels West. Caine Tower was built in 2000 consists of 1 blocks, 28 floors and has a total of 84 units. Caine Tower is located in School Net 11.
ZH 景怡居是位于西半山的单幢式大厦，于2000年落成，共建有1座，28层及84个单位。景怡居位处11校网。
Μεταγραφή jǐng yí jū shì wèi yú xī bàn shān de dān chuáng shì dà shà， yú2000nián luò chéng， gòng jiàn yǒu1zuò，28céng jí84gè dān wèi。jǐng yí jū wèi chù11xiào wǎng。
EN Euston Court Tower 1 is a/an Estate located at Mid-Levels West. Euston Court Tower 1 was built in 1989 consists of 30 floors and has a total of 236 units. Euston Court Tower 1 is located in School Net 11.
ZH 豫苑 1座是位于西半山的屋苑，于1989年落成，共建有30层及236个单位。豫苑 1座位处11校网。
Μεταγραφή yù yuàn 1zuò shì wèi yú xī bàn shān de wū yuàn， yú1989nián luò chéng， gòng jiàn yǒu30céng jí236gè dān wèi。yù yuàn 1zuò wèi chù11xiào wǎng。
EN Beaudry Tower is a/an Stand-alone Building located at Mid-Levels West. Beaudry Tower was built in 1989 consists of 1 blocks, 32 floors and has a total of 93 units. Beaudry Tower is located in School Net 11.
ZH Beaudry Tower是位于Mid-Levels West的Stand-alone Building，于1989年落成，共建有1座，32层及93个单位。Beaudry Tower位处11校网。
Μεταγραφή Beaudry Tower shì wèi yúMid-Levels West deStand-alone Building， yú1989nián luò chéng， gòng jiàn yǒu1zuò，32céng jí93gè dān wèi。Beaudry Tower wèi chù11xiào wǎng。
| Αγγλικά | κινέζικα |
|---|---|
| of | 的 |
EN Lyttelton Garden Tower 2 is a/an Estate located at Mid-Levels West. Lyttelton Garden Tower 2 was built in 1993 consists of 31 floors and has a total of 62 units. Lyttelton Garden Tower 2 is located in School Net 11.
ZH Lyttelton Garden Tower 2是位于Mid-Levels West的Estate，于1993年落成，共建有31层及62个单位。Lyttelton Garden Tower 2位处11校网。
Μεταγραφή Lyttelton Garden Tower 2shì wèi yúMid-Levels West deEstate， yú1993nián luò chéng， gòng jiàn yǒu31céng jí62gè dān wèi。Lyttelton Garden Tower 2wèi chù11xiào wǎng。
| Αγγλικά | κινέζικα |
|---|---|
| of | 的 |
EN Unique Tower is a/an Stand-alone Building located at Happy Valley. Unique Tower was built in 1982 consists of 1 blocks, 23 floors and has a total of 92 units. Unique Tower is located in School Net 12.
ZH 旭逸阁是位于跑马地的单幢式大厦，于1982年落成，共建有1座，23层及92个单位。旭逸阁位处12校网。
Μεταγραφή xù yì gé shì wèi yú pǎo mǎ de de dān chuáng shì dà shà， yú1982nián luò chéng， gòng jiàn yǒu1zuò，23céng jí92gè dān wèi。xù yì gé wèi chù12xiào wǎng。
EN Race Tower is a/an Estate located at Happy Valley. Race Tower was built in 1990 consists of 1 blocks, 23 floors and has a total of 23 units. Race Tower is located in School Net 12.
ZH 駿馬閣是位于跑馬地的屋苑，于1990年落成，共建有1座，23层及23个单位。駿馬閣位处12校网。
Μεταγραφή jùn mǎ gé shì wèi yú pǎo mǎ de de wū yuàn， yú1990nián luò chéng， gòng jiàn yǒu1zuò，23céng jí23gè dān wèi。jùn mǎ gé wèi chù12xiào wǎng。
EN Village Tower is a/an Stand-alone Building located at Happy Valley. Village Tower was built in 1972 consists of 1 blocks, 26 floors and has a total of 104 units. Village Tower is located in School Net 12.
ZH 山村大廈是位于跑馬地的單幢式大廈，于1972年落成，共建有1座，26层及104个单位。山村大廈位处12校网。
Μεταγραφή shān cūn dà shà shì wèi yú pǎo mǎ de de dān chuáng shì dà shà， yú1972nián luò chéng， gòng jiàn yǒu1zuò，26céng jí104gè dān wèi。shān cūn dà shà wèi chù12xiào wǎng。
Εμφάνιση 50 από 50 μεταφράσεων
Παρόμοιες μεταφράσεις
clock clock date calendar clock clock clock tower bern's clock tower clock countdown clock round the clock around the clock alarm clock employees clock team clock clock service table clock clock hours internal clock target clock frequency clock as soon o’clock wall clock clock customer clock out o‘clock o'clock clock uptime sla o clock correct clock generator clock to deliver rtc clock verification ptp clock manager spread spectrum clock precision master clock alarm clock xtreme chess clock icons clock timing solutions clock on wall reduce clock flower clock clock tree design clock synthesizer clock generators clock buffers clock synthesizers clock position clock for identifying ansys clock fx multiplexers join clock oscillators pcie clock a specific clock clock speeds a clock servo
Άραβας
Βιετναμέζικα
Γερμανός
Ιαπωνικά
Ινδονησιακά
Ισπανικά
Νορβηγός
Ολλανδός
Πορτογαλικά
Ρωσική
Σουηδικά
Στίλβωση
Τσέχος
γαλλική γλώσσα
ιταλικός
κινέζικα
κορεάτης
ουγγρικός
τούρκικος
φινλανδικός